Sr. Staff Engineer, CPU MidCore RTL Design
About The Position
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented Design Verification engineer to join our CPU design team to define and implement the MidCore block for high-performance CPUs. You’ll work on a from-scratch CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Requirements
- Experienced in Out-of-Order CPU microarchitecture with expertise in Rename, Scheduler, ROB, and Datapath.
- Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
- Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
- Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.
Responsibilities
- Own RTL design and microarchitecture development for a portion of the MidCore block of a high-performance RISC-V CPU.
- Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals.
- Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
- Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
- Enhance RTL design environment, tools, and methodologies to improve development efficiency.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
