Tenstorrent-posted about 1 month ago
$100,000 - $500,000/Yr
Full-time • Mid Level
Hybrid • Santa Clara, CA
501-1,000 employees
Professional, Scientific, and Technical Services

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're building verification infrastructure from scratch for high-performance RISC-V CPU clusters and SoCs. This role owns the system-level DV strategy, verifying how multiple IPs interact across caches, NoCs, coherence protocols, and memory hierarchies. You'll define verification plans, architect UVM environments, and drive coverage closure for features that span the entire cluster. If you think in terms of systems, not just blocks, and want to shape methodology on a ground-up CPU program-this is it. This is a hybrid role in Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
  • Strong experience with SystemVerilog and UVM-based verification.
  • Proven ability to drive subsystem or SoC-level DV projects with integration and system feature validation responsibilities.
  • Familiarity with AXI/CHI protocols, system IP flows (debug/trace, power management), and integration flows for multi-IP verification environments.
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