Qualcomm-posted 5 months ago
$198,700 - $298,100/Yr
Full-time • Mid Level
Remote • Santa Clara, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing

Hiring in San Diego, Santa Clara and Austin. NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support the world's best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area.

  • Develop, integrate and release new features in our high-performance place-and-route CAD flow
  • Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
  • Maintain, support and debug implementation flows, and resolve project-specific issues
  • Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA
  • Work with EDA vendors to define roadmap and to resolve tool issues
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
  • OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
  • Masters degree in Electrical/Electronics Engineering or Computer Science
  • Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role
  • High level of proficiency in Tcl as well as Python
  • Experience with automation
  • Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV
  • Experience with advanced technology nodes (5nm or lower)
  • Solid understanding of digital design, timing analysis and physical verification
  • Strong user of industry-standard place-and-route tools such as Cadence Innovus
  • Proven track record of managing and regressing place-and-route flows
  • Competitive annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Highly competitive benefits package designed to support your success at work, at home, and at play
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service