Sr. Staff ASIC Verification Engineer

Rivian • Palo Alto, CA

1d • $237,000 - $296,000

About The Position

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.
As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Role Summary

We are seeking a high-caliber Sr. Staff Verification Engineer to join our Automotive Silicon team. You will be responsible for the end-to-end functional verification of our next-generation ADAS SoC. Your mission is to ensure our silicon meets the highest automotive safety integrity levels through rigorous constrained-random verification, formal methods, and fault injection campaigns.

Requirements

• Experience: Typically 10+ years of industry experience in ASIC design verification. Engineers who have seen multiple chips from "concept to tape-out."
• Education: BS/MS or PhD in Electrical Engineering or Computer Engineering.
• Hardware Knowledge: Deep understanding of Computer Architecture.
• Memory hierarchies (Cache, DMA, and DDR/HBM).
• Interconnect protocols (NoC - Network on Chip).
• Low-power design verification (UPF/CPF).

Nice To Haves

• Specialized hardware like Systolic Arrays, Vector Processors, or Neural Processing Units (NPUs).
• Understanding of how CNN and Transformer networks map to hardware.
• Compilers and toolchains

Responsibilities

• Safety-Critical Verification: Develop and execute verification plans compliant with ISO 26262 standards. Conduct Fault Injection Analysis (FIA) to verify safety mechanisms (ECC, Parity, BIST).
• Chiplet & Interconnect Verification: Architect UVM environments to verify Die- to-Die (D2D) interfaces using standards like UCIe or BoW. Ensure data integrity and low-latency communication across multiple chiplets.
• Testbench Development: Build scalable, reusable SystemVerilog/UVM testbenches at the block, subsystem, and SoC levels.
• Advanced Methodologies: Implement Coverage-Driven Verification (CDV) and use Formal Verification (SVA) to exhaustively prove corner cases in safety-critical arbiters and state machines.
• Hardware-Software Co-Verification: Collaborate with firmware teams to run C- based tests in a UVM environment to verify boot sequences and hardware abstraction layers.

Benefits

• We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees.
• You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements.
• Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment.
• More information about benefits is available at rivianbenefits.com.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level