Sr. STA Engineer

Intel

3d•Remote

About The Position

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We are seeking a highly skilled and hands-on Timing Doer to join our full-chip timing team. This role is critical to achieving top-level timing closure for complex SoC/ASIC designs. The ideal candidate is a technical expert in STA, scripting, and timing infrastructure, capable of driving timing accuracy, automation, and scalability across the full chip.

Requirements

Bachelors in Electrical Engineering, Computer Engineering, or STEM field with 9+ years or Masters Electrical Engineering, Computer Engineering, or STEM field & 6+ years or PhD Electrical Engineering, Computer Engineering, or STEM field & 4+ years of industry experience.
7+ years of industry experience in Complex CPU/SOC/ASIC/FPGA implementation and timing closure.
5+ years in STA signoff tools like Prime Time, Constraint generation and verification tool like Fishtail.
3+ years scripting skills in TCL/Python/Perl/Shell.
3+ years of RTL Design Development and physical implementation.

Nice To Haves

Strong expertise in Static Timing Analysis (Primetime, Tempus, etc.)
Proficiency in scripting languages: Tcl, Python, shell.
Deep understanding of PVT corners, library modeling, and timing abstraction.
Experience with timing ECOs, report analysis, and flow automation.
Ability to manage and scale timing environments across large designs.
Excellent problem-solving and debugging skills.
Strong communication and collaboration abilities.
Experience in full-chip timing closure for advanced SoC/ASIC nodes.
Familiarity with hierarchical STA and timing model generation.
Knowledge of physical design flows and layout impact on timing.
Exposure to version control systems and CI/CD for EDA environments.

Responsibilities

Full-Chip STA Execution: Run and maintain top-level timing analysis across all modes and corners using tools like Primetime.
Timing Coverage and Quality: Ensure every path is timed correctly; track and improve timing quality metrics such as coverage, margin distribution, and skew.
Tool and Environment Management: Maintain and update STA tool versions and patch releases. Seamlessly roll out PVT corner changes and scaling methods for unsupported libraries.
Automation and Scripting: Develop robust scripts (Tcl, Python, shell) to automate STA runs, report generation, ECO flows, and environment setup. Create scalable and reusable infrastructure for timing tasks.
Library and Corner Handling: Implement scaling techniques for missing libraries. Rapidly adjust PVT corners and integrate changes into the flow.
Collaboration and Support: Work closely with timing owners and block teams to resolve cross-boundary timing issues. Provide infrastructure and tooling support to timing owners.
Signoff Readiness: Ensure timing signoff criteria are met across all corners and modes. Validate timing post-ECO and post-layout. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Find out more about the benefits of working at Intel.

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