Sr. RFIC - PLL Design Engineer
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About The Position
As a Senior RFIC-PLL Designer at Apple, you will play a pivotal role in the wireless silicon development team, focusing on the design and validation of radio transceivers integrated into complex wireless System on Chips (SoCs). This position is critical in ensuring that Apple's state-of-the-art wireless connectivity solutions are successfully integrated into a wide range of products, impacting millions of users worldwide. You will be responsible for providing both analog and digital Phase-Locked Loop (PLL) solutions for wireless SoCs, driving these designs through to mass production for Apple's Wireless Connectivity products. Your responsibilities will include leading the design of radio transceiver chains, which encompass analog PLLs, Voltage-Controlled Oscillators (VCOs), digital PLLs, and various components in the receive (RX) and transmit (TX) paths. You will be tasked with driving key performance indicators (KPIs) such as power consumption, area, and overall performance to meet product requirements. Collaboration will be essential, as you will work closely with cross-functional teams, including platform architecture, wireless design, and RF hardware and software teams, to define innovative radio features. In this role, you will engage in hands-on design contributions, starting from the conceptual phase through to architecture and topology development, conducting transistor-level feasibility studies, and performing KPI trade-off analyses. You will also design RF and analog loopbacks for calibration and compensation, address co-existence scenarios, and ensure successful tape-out by overseeing floorplan layout and verification processes. Your collaboration with RFIC test engineers will be crucial during the bring-up, debugging, and optimization phases of the wireless connectivity chip, ensuring compliance with specifications for volume production.
