Blue Origin-posted 2 days ago
Full-time • Mid Level
Onsite • Seattle, CA
5,001-10,000 employees

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! This role is part of Blue Origin corporate functions, providing centralized support across Blue Origin business unit teams, functions, and locations. At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! This is a foundational role in our Emerging Systems team. To further Blue Origin's mission of millions of people living and working in space for the benefit of Earth, we are bringing together technology from across our product lines to build the future of space-based communication. This role may be located onsite in Bay Area, CA. Candidates residing in or relocating to that location are approved for a temporary remote work exception while our local site is developed.

  • Lead the custom silicon technical strategy and architecture for a first-of-its-kind mission critical communications network
  • Execute complete partition synthesis and physical implementation workflows including synthesis, floorplanning, power/ground grid generation, place and route, and various signoff checks
  • Define and execute a comprehensive verification and validation strategy with DFT and DFM feedback loops
  • Create and enhance physical design methodologies and develop automation scripts to optimize implementation processes
  • Partner with ASIC design teams to conduct architectural feasibility studies, establish timing/power/area targets, and evaluate RTL design tradeoffs
  • Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering
  • Identify and resolve complex design challenges related to timing, congestion, and workflow bottlenecks
  • Perform detailed debugging and closure of signoff issues in static timing analysis (STA), noise analysis, logic equivalency checking, physical verification, and power integrity
  • Support lab integration and troubleshooting activities
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
  • 10 plus years of hardware engineering experience
  • Experience with FPGA and/or ASIC design
  • Proficiency in HDL programming (VHDL, Verilog, and/or SystemVerilog)
  • Experience with Linux development environment
  • Experience with design verification and test bench development
  • Advanced degree (MS/PhD) in Electrical Engineering, Computer Engineering, or related field
  • Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
  • Experience with Software-Defined Radio Architectures, ADC/DAC, and/or DSPs
  • Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM)
  • Strong object-oriented programming and scripting skills (Python, TCL, Perl)
  • Experience with physical design flows and industry-standard EDA tools
  • Experience with RTL2GDSII physical design and signoff flows
  • Knowledge of deep sub-micron FinFET and CMOS technologies
  • Experience with DFT/Scan/MBIST/LBIST methodologies
  • Experience mentoring junior engineers
  • Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
  • Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
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