Cadence-posted 6 months ago
$154,000 - $286,000/Yr
Full-time • Senior
San Jose, CA
5,001-10,000 employees
Ambulatory Health Care Services

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets.

  • Enhancing and expanding the existing tools' architecture to cover timing analysis
  • Creating new frameworks for analysis of effects dominant at n5 and below
  • Using machine learning technology to bring order of magnitude speed / capacity / usability improvements over existing solutions
  • 8+ years of experience in development of EDA tools and one or more of transistor level timing, power, noise, aging, reliability, and emir analysis
  • Hardcore C++ Knowledge - Linux
  • Proficiency designing data structures, algorithms, and software engineering principles
  • Industry experience developing and maintaining C++ based applications on a Unix or Linux environment
  • Experience with quality and software processes
  • Proficiency in analyzing transistor or gate level schematics
  • The preferred candidate is expected to have a BS in CS/EE/CE
  • Experience in development of circuit simulation or library characterization programs
  • High level understanding of SPICE simulation transistor models
  • Experience with distributed programming, database design, and cloud APIs for distributed computing
  • Paid vacation and paid holidays
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • A variety of medical, dental and vision plan options
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