Sr. Principal DSP Architect
About The Position
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As a Sr. Principal DSP Architect, you will join a team of DSP/Systems experts, digital designers, and mixed-signal design engineers developing advanced DSP SerDes for next generation 400G per lane wireline and optical interconnect for AI systems. The DSP architecture team is responsible for the following job functions. Research novel modulation, equalization, and FEC techniques for 400G per lane wireline and optical systems. Create DSP and FEC algorithms, bit/cycle accurate C/C++ models, and hardware block specifications appropriate for RTL implementation. Work with digital team/firmware team to optimize and implement DSP algorithms in hardware/firmware. Hands-on involvement in post-silicon performance tuning and optimization. Provide guidance on test plans for lab characterization. Provide support for internal customers deploying SerDes IP.
Requirements
- Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience with DSP architectures and algorithm development.
- Solid understanding of and experience with designing adaptive DSP algorithms.
- Solid understanding of and experience with the practical aspects of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation.
- Good programming skills in C/C++, Matlab or Python.
- Experience in guiding and testing the transfer of high-speed numerical algorithms from C/C++ to Verilog.
Nice To Haves
- Familiarity with high-speed optical and electrical channels and the DSP algorithms for compensating their impairments.
- Reading knowledge of Verilog RTL and the ability to assist with the assessment of Verilog implementations of DSP algorithms.
- Experienced with modern version control and software management systems.
- Experience with error correction (Reed-Solomon, BCH, soft decoding) in high-throughput, low-latency systems.
Responsibilities
- Research novel modulation, equalization, and FEC techniques for 400G per lane wireline and optical systems.
- Create DSP and FEC algorithms, bit/cycle accurate C/C++ models, and hardware block specifications appropriate for RTL implementation.
- Work with digital team/firmware team to optimize and implement DSP algorithms in hardware/firmware.
- Hands-on involvement in post-silicon performance tuning and optimization.
- Provide guidance on test plans for lab characterization.
- Provide support for internal customers deploying SerDes IP.
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What This Job Offers
Job Type
Full-time
Career Level
Principal
Number of Employees
251-500 employees
