At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. We're doing work that matters. Help us solve what others can't.
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Job Type
Full-time
Career Level
Mid Level
Industry
Ambulatory Health Care Services
Education Level
No Education Listed
Number of Employees
5,001-10,000 employees