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As a Senior Manager of Silicon Validation at Synopsys, you will lead a dedicated team of engineers focused on post-silicon electrical validation and debugging of mixed-signal PCIe SerDes IP. This role is pivotal in ensuring the performance and reliability of our silicon products, which are integral to the development of advanced technologies such as self-driving cars, artificial intelligence, and 5G. You will oversee the development of evaluation scripts, validate circuit block behavior, and evaluate results while debugging issues in a research and development test lab environment. Your leadership will be crucial in managing schedules and resources to ensure timely and efficient execution of validation activities. Collaboration is key in this role, as you will work closely with both internal and external teams to develop comprehensive test plans and analyses. You will also be responsible for post-silicon validation and debugging of die-to-die interface IP products targeting the UCIe protocol. This includes tool development for product testing, data presentation, research, and report generation. You will help develop sophisticated software solutions to evaluate silicon performance on hardware, ensuring that our products meet the unique performance, power, and size requirements of our customers' applications. At Synopsys, we pride ourselves on being at the forefront of innovation, and your contributions will directly impact the development of cutting-edge technologies that shape the future. We are looking for a candidate who shares our passion for innovation and is eager to make a difference in the world of silicon IP.
