Sr. Logic Design (RTL) Engineer
Capgemini•Santa Clara, CA
443d
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About The Position
The Sr. Logic Design (RTL) Engineer at Capgemini is responsible for detailed block design based on system requirements and specifications. This role involves RTL coding, performing lint checks, CDC tests, and creating timing constraint files. The engineer will collaborate closely with various teams including Synthesis, STA, PD, and DFT to ensure all functional requirements, performance, power, and area goals are met.
