Capgemini-posted about 1 year ago
Full-time • Senior
Santa Clara, CA
10,001+ employees
Professional, Scientific, and Technical Services
This job is no longer available
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The Sr. Logic Design (RTL) Engineer at Capgemini is responsible for detailed block design based on system requirements and specifications. This role involves RTL coding, performing lint checks, CDC tests, and creating timing constraint files. The engineer will collaborate closely with various teams including Synthesis, STA, PD, and DFT to ensure all functional requirements, performance, power, and area goals are met.
