Sr. DFT Design Engineer, AWS Machine Learning Acceleration

Amazon • Austin, TX

91d • $143,300 - $247,600

About The Position

AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. As a member of the Silicon Optimization Engineering Team you’ll be responsible for the design and optimization of hardware in our data centers. You’ll provide leadership in the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology areas. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve your products performance, quality and cost. We’re changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Requirements

• BS degree in EE, CE, or CS
• 5+ years of practical DFT experience with large processor and/or SoC designs
• Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
• Experience with automation script development

Nice To Haves

• MS degree in EE, CE or CS
• Good breadth of knowledge in chip design from micro-architecture through physical design
• Good knowledge of design verification (DV) simulation methodologies
• Experience with large gate-level simulation setup and debug with SDF
• Strong programming and scripting skills in Perl, Python or Tcl
• Experience with industry standard DFT/SCAN/ATPG tools
• Experience with STA constraints development and analysis for DFT modes
• Practical experience with silicon debug

Responsibilities

• Develop, implement and verify state-of-the-art Design for Test (DFT) architectures
• Work with block designers to integrate DFT implementations
• Work with physical design team to setup and implement DFT insertion flow
• Develop high coverage and cost effective DFT methodologies
• Perform RTL coding and Verification
• Participate in Silicon debug and write scripts to effectively handle ATE related data
• Communicate and work with team members across multiple disciplines

Benefits

• Medical, financial, and/or other benefits
• Equity and sign-on payments may be provided as part of a total compensation package

What This Job Offers

• Education Level: Bachelor's degree