Sr. ASIC Layout Design Engineer

Teledyne Technologies • Goleta, CA

1d

About The Position

We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These chips form the heart of our infrared detectors, sensors, and cameras—used in applications ranging from firefighting and security to scientific research and government contracts. As part of our close-knit team, you will play a key role in producing analog and mixed-signal circuit layouts by preparing multi-dimensional, detailed drawings of the semiconductor devices from schematics provided by design engineering. You will collaborate closely with analog and digital circuit designers, ensuring precision in signal integrity, parasitic coupling, and matched transistor pairs. From initial design discussions to final tape-out, your expertise will help shape industry-leading imaging technology. Must be US Citizen or PERM Resident

Requirements

• Bachelor’s degree in engineering or related field with 10+ years of industry experience
• Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes
• Proficiency in Cadence Virtuoso XL for connectivity-aware design
• Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques
• Experience with custom cell-based layout and top-level floor planning, with work on focal-plane arrays a plus
• Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects
• Excellent communication skills and the ability to work effectively within a multidisciplinary team
• Programming/scripting skills in SKILL, TCL, Shell, or Python

Responsibilities

• Develop high-quality analog/mixed-signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools.
• Collaborate with circuit designers to optimize floor-planning, placement, and routing.
• Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and the use of Process Design Kits (PDK).
• Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance, manufacturability and yield.
• Present weekly updates to project schedule and percent task completions.
• Prepare reports for design reviews and internal and external customer presentations.
• Perform proper handling of Export Controlled Information and exercise discipline in following GTC protocol and jurisdictional classification.
• Release and maintain design documents per the ISO quality system requirements.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 101-250 employees