Tensordyne-posted 3 months ago
Full-time • Senior
Sunnyvale, CA

In this hands-on, technology leadership role, you will lead EDA tools, DevOps systems, and associated engineering workflow development for Tensordyne's multimodal generative AI inference acceleration products. As a valued senior member of our ASIC team, you will guide and assist your colleagues to help improve and invent EDA workflows and DevOps systems within a fast-paced, agile HPC development environment that utilizes EDA tools from external companies like Cadence and as well as internally developed workflows. You will drive Tensordyne’s optimization, implementation and exploration of new EDA tools and technologies for the full ASIC chip design process. Your contributions will continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of Tensordyne products. This is a hands-on role that’s ideal for ASIC EDA experts who have a multi-disciplinary engineering/DevOps background, along with a keen interest in generative AI, and a passion for designing, debugging, optimizing and finding creative EDA solutions to complex technical challenges. In this role, you will work very closely with your ASIC team members who are engaged in the design and verification of Tensordyne products, to understand and improve their workflows and EDA needs.

  • Lead EDA tools and DevOps systems development for multimodal generative AI inference products.
  • Guide and assist colleagues in improving and inventing EDA workflows and DevOps systems.
  • Drive optimization, implementation, and exploration of new EDA tools and technologies for ASIC chip design.
  • Innovate and improve scalable, reliable, high-performance systems and tools.
  • Collaborate closely with ASIC team members to understand and improve their workflows and EDA needs.
  • 10+ years expert level knowledge of Linux system administration.
  • Familiarity with cloud-based DevOps (IaC, CaC, etc.) and experience supporting EDA tools in a cloud-based environment.
  • Experience leading development and support for compilation, build automation, testing, packaging, and installation project generators.
  • Hands-on ASIC engineering experience, including knowledge of VLSI/SoC chip design and verification workflows.
  • Programming and debugging skills with SystemVerilog and key languages like C/C++, Perl, TCL, and Python.
  • Prior work experience with onboarding and supporting ASIC engineers with EDA workflows.
  • Excellent analytical, written, and verbal interpersonal skills.
  • Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.
  • Comprehensive benefits
  • Competitive compensation
  • Flexible spending options
  • Recognition programs
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