Sr. Analog Frontend Design Automation Engineer

Solidigm•Rancho Cordova, CA

About The Position

We are seeking a Senior Analog Frontend Design Automation Engineer to accelerate analog and mixed-signal design productivity by building and owning robust, validated simulation and analysis flows and integrating them into a scalable custom CAD environment. This role is hands-on and highly cross-functional, partnering closely with analog designers, AMS verification, reliability, and PDK teams to standardize workflows and improve quality, repeatability, and simulation-to-silicon correlation. The ideal candidate brings strong experience in custom CAD enablement (Virtuoso-based environments), SPICE simulation automation, and reliability/EMIR-aware methodologies, with the ability to translate real designer pain points into practical tools, frameworks, and flow improvements. We are seeking a Senior Analog Frontend Design Automation Engineer to accelerate analog and mixed-signal design productivity by building and owning robust, validated simulation and analysis flows and integrating them into a scalable custom CAD environment. This role is hands-on and highly cross-functional, partnering closely with analog designers, AMS verification, reliability, and PDK teams to standardize workflows and improve quality, repeatability, and simulation-to-silicon correlation. The ideal candidate brings strong experience in custom CAD enablement (Virtuoso-based environments), SPICE simulation automation, and reliability/EMIR-aware methodologies, with the ability to translate real designer pain points into practical tools, frameworks, and flow improvements.

Requirements

BS/MS in EE/CE or related field (or equivalent experience).
Strong background in analog/mixed-signal design principles and understanding of the analog IC design flow (schematic → simulation → layout/verification).
Hands-on experience with SPICE simulation tools and modeling/analysis techniques used in analog validation.
Proven ability to build automation for analog workflows: corner/MC management, run orchestration, regression scaling, standardized reporting.
Working knowledge of physical signoff concepts that impact analog results, including parasitic extraction, DRC/LVS, and EM/IR fundamentals.
Strong scripting/automation skills (Skill/Tcl/Perl/Python or equivalent) and ability to deliver production-quality tools.
Demonstrated ability to collaborate across teams and convert ambiguous requirements into clear, usable solutions.

Nice To Haves

Experience in Custom CAD / Virtuoso platform enablement, including Skill-based automation and flow integration.
Experience supporting reliability / ERC / PERC-type flows and methodology integration into custom design environments.
Familiarity with AMS verification environments and cross-domain debug (analog + digital interfaces).
Exposure to digital/FPGA prototyping and mixed-signal integration—useful for improving end-to-end validation workflows. (Candidate-aligned enhancement; not required.)

Responsibilities

Simulation & Methodology Enablement Develop and maintain validated SPICE simulation flows (e.g., HSPICE/Spectre-class), including run templates, corner setups, Monte Carlo sampling schemes, and convergence guidelines.
Create standardized workflows for analog blocks (e.g., sense amplifiers, charge pumps, references, HV switching circuits), enabling repeatable setup and trustworthy results across projects.
Drive simulation-to-silicon correlation by aligning device models, PVT corners, and simulation assumptions to the PDK; identify mismatches and coordinate improvements.
Custom CAD / Virtuoso Automation Build and support custom CAD automation spanning schematic entry, testbench generation, run orchestration, results harvesting, and regression execution, emphasizing reproducibility and ease-of-use.
Develop scripts/tools (Skill/Tcl/Perl/Python or equivalent) to automate repetitive tasks, reduce manual errors, and improve designer throughput.
Provide end-user support and documentation (best practices, templates, debug playbooks) to reduce flow friction and improve adoption.
Reliability / EMIR / Extraction-aware Enablement (Frontend Focus) Enable flows that connect simulation with layout-derived effects—supporting workflows that incorporate parasitics and reliability considerations (e.g., extraction-aware simulation readiness, EM/IR-aware checks, reliability/ERC integration).
Collaborate with layout/verification/reliability partners to improve clarity and consistency of rule interpretation and analysis setup where needed.
Cross-Functional Leadership Partner with analog design, AMS verification, PDK/library teams, and broader DA infrastructure to deliver standardized methodologies and scalable flow deployment.
Contribute to DA standards (methodology, signoff expectations where applicable, and flow QA/regression practices) to reduce late-cycle churn and risk.