Spacecraft Timing System Engineer

Logos Space•Mountain View, CA

About The Position

Logos Space is building a proliferated Low Earth Orbit (pLEO) constellation to deliver resilient, high-performance connectivity to enterprise and government users worldwide. As part of that effort, the Navigation team is designing and building the software and infrastructure for spacecraft timing, astrodynamics, orbit determination, and related navigation workflows used across flight and ground systems. The Navigation team at Logos Space is building the timing foundation that realizes and maintains trusted onboard time, supports calibration and observability, and provides trusted timing interfaces to adjacent flight and payload systems. This role focuses on designing, implementing, and validating the timing capabilities needed to achieve nanosecond-class onboard timing accuracy on the spacecraft. It sits at the intersection of timing and synchronization, FPGA and embedded implementation, digital hardware, calibration, and validation. Depending on level, you will contribute to or independently own well-scoped portions of the timing stack, such as timing measurement and timestamping, clock control and steering, timing distribution, monitoring and telemetry, calibration workflows, or validation and automation infrastructure. We are looking for engineers who can work well in a fast-paced environment, turn incomplete requirements into practical software, and collaborate closely with adjacent teams.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, Computer Science, Aerospace Engineering, or a related STEM field, or equivalent practical experience.
2+ years of relevant professional experience building timing or synchronization systems, FPGA/RTL, embedded systems, digital hardware, avionics, telecom timing, scientific instrumentation, or similar high-reliability systems. Strong graduate research or project experience may substitute for some professional experience.
Hands-on experience implementing or validating timing or synchronization functionality in FPGA/RTL or similarly timing-critical digital systems.
Proficiency in VHDL, Verilog, or SystemVerilog.
Proficiency in Python for automation, lab tooling, and data analysis.
Working knowledge of timing and synchronization fundamentals, including clock generation and distribution, timestamping, oscillator behavior, phase/frequency alignment, jitter, latency, determinism, holdover, and calibration or monitoring concepts.
Experience with FPGA toolchains and workflows, including simulation, synthesis, place-and-route, timing analysis, and lab bring-up.
Experience debugging FPGA or digital hardware in the lab using oscilloscopes, logic analyzers, spectrum analyzers, time-interval measurement tools, or similar instrumentation.
Familiarity with Linux-based development environments, Git, and automated testing.
Strong written and verbal communication skills.

Nice To Haves

4+ years of relevant experience and the ability to independently own technical workstreams.
Experience building or validating nanosecond-class timing or synchronization systems for space, avionics, telecom, networking, scientific instrumentation, or defense applications.
Experience with time-transfer or external timing references such as GNSS-based timing, 1PPS / 10 MHz distribution, PTP / White Rabbit, common-view, two-way time transfer, or similar techniques.
Experience with clock characterization, frequency-stability analysis, phase-noise or jitter measurements, Allan deviation, oscillator trade studies, or holdover evaluation.
Experience with clock steering, servo design, or estimation methods applied to timing systems.
Experience with embedded firmware or low-level software for device control, board bring-up, telemetry, and calibration workflows.
Experience with board-level digital or mixed-signal hardware design, schematic review, clock-tree or oscillator circuitry, or hardware bring-up.
Experience with space, defense, or other reliability-critical electronics, including radiation-tolerant or fault-tolerant design considerations.
Experience interfacing timing systems with GNSS receivers, flight computers, communications payloads, signal-generation chains, or RF timing paths.

Responsibilities

Develop and maintain in-house FPGA/RTL, embedded logic, and supporting software for spacecraft timing and synchronization.
Design and implement timing-system functionality, including timing measurement, timestamping, clock control, timing distribution, calibration, telemetry, and monitoring.
Define and implement clean hardware/software interfaces, including registers, configuration, telemetry, fault and status signaling, and test hooks.
Contribute to timing-system architecture, requirements, partitioning, and trade studies in collaboration with electrical, embedded, GNSS, signal, flight software, and integration engineers.
Build simulation, testbench, replay, lab-validation, and automation infrastructure to verify correctness, stability, and timing performance.
Characterize timing performance, including accuracy, stability, jitter, phase alignment, latency, deterministic behavior, holdover, reacquisition, and calibration drift.
Contribute to timing error budgets and closure analyses for onboard time realization and interfaces to adjacent spacecraft or payload systems.
Build Python and/or C/C++ tools for bring-up, telemetry capture, calibration workflows, automation, and rapid debugging.
Support hardware bring-up, software-in-the-loop, hardware-in-the-loop, integrated test campaigns, and anomaly investigations.
For more experienced candidates, independently own a small timing subsystem or validation pipeline end-to-end and drive clarity of interfaces across adjacent teams.