Software Intern

Cadence Design Systems • San Jose, CA

2d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is searching for a Software Engineer to work on delay calculation and signal integrity (SI) analysis in Static Timing Analysis tool. Responsible for implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits, investigating techniques to improve correlation of delay/SI analysis to SPICE, and modeling of nanometer circuit effects in delay/SI analysis. We’re doing work that matters. Help us solve what others can’t. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Requirements

• The candidate should have MS/PhD in EE/CS or related discipline
• Strong programming skills in C++
• Deep familiarity with object-oriented programming methods

Nice To Haves

• Prior knowledge and experience with multi-threaded programming
• Numerical analysis techniques
• Delay calculation methods for nanometer circuits preferred

Responsibilities

• Implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits
• Investigating techniques to improve correlation of delay/SI analysis to SPICE
• Modeling of nanometer circuit effects in delay/SI analysis

What This Job Offers

• Career Level: Intern
• Number of Employees: 5,001-10,000 employees