Software Architect FPGA

Advanced Micro Devices-posted 3 months ago
Mid Level
Hybrid • San Jose, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. We are seeking a highly experienced and motivated FPGA Software Architect to join our team in a key individual contributor role, with a strong potential to grow into a leadership position. This role focuses on the development and architecture of internal EDA tools with a deep emphasis on timing analysis, static timing analysis (STA), timing closure, and FPGA-specific clocking and configuration architectures.

  • Design and architect software systems specifically targeting FPGA timing analysis and closure.
  • Development of internal EDA tools for static timing analysis (STA).
  • Clock tree modeling, propagation, and clock domain crossing analysis.
  • Support for timing closure workflows across hardware/software interfaces.
  • Collaborate closely with FPGA hardware architects and implementation teams to integrate hardware timing models into software frameworks.
  • Interpret hardware behavior for accurate software-level simulation and analysis.
  • Own the technical roadmap for timing-centric EDA software tools within the FPGA design flow.
  • Build scalable, modular, and high-performance software components for internal FPGA tools.
  • Drive system-level architectural decisions considering performance, usability, and maintainability.
  • Eventually lead and mentor a growing team of software and EDA engineers.
  • Stay abreast of developments in FPGA architectures, timing methodologies, and EDA toolchains, bringing insights back into the product.
  • Foster a culture of technical excellence, collaboration, and innovation.
  • Experience in software development, focused on FPGA or ASIC timing analysis and closure.
  • Expert-level understanding of FPGA architectures, including clocking structures and global/local routing.
  • Configuration memory and programmable logic blocks.
  • Timing constraints and analysis methodologies (e.g., SDC, STA).
  • In-depth experience with timing closure methodologies, including multi-corner, multi-mode (MCMM) analysis, false/exception path handling, and delay modeling.
  • Strong proficiency in software architecture and systems programming, with expertise in C++/Python and scalable system design.
  • Familiarity with parallel processing, memory optimization, and performance profiling.
  • Prior experience with developing or extending internal EDA tools for FPGA or ASIC design flows.
  • Proven ability to work effectively across disciplines (software, hardware, and architecture).
  • Comfortable in fast-paced, iterative development environments with high ownership.
  • Demonstrated ability or potential to lead engineering teams, set technical direction, and mentor junior engineers.
  • AMD benefits at a glance.
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