Synopsys-posted 3 months ago
Full-time • Senior
Hybrid • Colorado Springs, CO
Professional, Scientific, and Technical Services

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

  • Defining and tracking Verification test plans
  • Designing and writing constrained-random SystemVerilog testbenches using UVM
  • Writing SystemVerilog assertions
  • Writing functional coverage
  • Debugging RTL and GLS failures
  • Conducting code coverage analysis
  • Providing mentoring and guidance to less experienced team members
  • BSEE in Electrical Engineering with 10+ years of industry experience
  • Proficiency in digital verification in a UVM environment; formal verification experience is a plus
  • Knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture
  • Hands-on experience with verification tools such as VCS, waveform analyzer and VIP integration
  • Expertise in Verilog, SystemVerilog, and Perl/Python scripting
  • Comprehensive range of health, wellness, and financial benefits
  • Monetary and non-monetary offerings
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