SOC Engineering, Sr Manager

Synopsys-posted 3 months ago

$176,000 - $265,000/Yr

Full-time • Senior

Austin, TX

5,001-10,000 employees

Professional, Scientific, and Technical Services

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. Our System Solutions Group enables our customers with end-to-end SoC designs in advanced technologies. We deliver tool flows, provide expertise in design methodology creation and implementation, and support RTL-to-GDSII implementation for blocks, sub-systems, and full SoCs. Our customers range from start-ups to industry leaders, commercial and government agencies, developing products for high-performance computing, automotive, aerospace & defense, and more.

Manage and lead a team of 5-7 SoC/Subsystem Design Engineers for various customer engagements.
Work with Synopsys customers to understand their needs and define design scope and activities.
Lead and mentor a design team in day-to-day activities and grow the capabilities of the design team for future assignments.
Understand and apply modern design processes and flows for ASIC designs.
Partitioning and architecting designs from requirements, including high-level and microarchitecture.
Collaborating with cross-functional teams, including verification, DFT, and physical design.
Implementing industry-standard design methods for clocking, resets, metastability, and logical design for control/data paths.
Developing and reviewing System Verilog RTL code for complex designs.

Bachelor's or Master Degree in Electrical or Computer Engineering.
12+ years of experience designing and verifying ASIC/FPGA devices.
Proficiency in System Verilog RTL coding and review.
Experience with vendor tooling within an ASIC development flow (Simulators, LINT, CDC/RDC, Synthesis, STA).
Ability to understand and implement complex protocols such as PCIe, Ethernet, UCIe.

Comprehensive health, wellness, and financial benefits.
Eligibility for an annual bonus, equity, and other discretionary bonuses.

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