SOC Design Engineer

Marvell Technology • Westborough, MA

69d • $100,400 - $148,630

About The Position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex System-on-Chip (SOCs), from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The SOC Design team is a critical part of this group, responsible for building the most complex SOCs, integrating both internal and external IPs and driving a high quality design tape-out for the CCS products. As part of SOC Design team, you will play a key role in building complex multi-chiplet SOCs for CCS product portfolio.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 2+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields and 1+ years of related professional experience.
• Relevant experience in design engineering with focus on SOC design, integration and verification.
• Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc.
• Hands on experience with RTL Coding and methodologies, IP integration flows, design quality tools.
• Hands on experience in one or more areas of SOC design components and interconnects, including clock, reset, design-for-test and design-for-debug features, IP integration and boot and security requirements.
• Working knowledge in one or more of the following: Processor architecture, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM).
• Experience in working with cross-functional teams across multiple geographies.

Responsibilities

• Work with SOC Integration team to integrate internal and external IP blocks at the chip level.
• Collaborate with cross-disciplinary team including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements to tape-out a high quality, zero-defect product.
• Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip level.
• Lead design effort for internally developed processor IP blocks to meet specific architectural needs.
• Work closely with verification and implementation teams to meet product requirements.
• Deliver micro-architectural specifications for these designs.
• Utilize and participate in the development of automation tools to accelerate the pace of development.
• Leverage next-generation AI tools to enhance existing work flows.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

What This Job Offers

• Career Level: Entry Level
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees