SoC Architect – PCIe/CXL/UAL/DMA

Advanced Micro Devices, Inc•San Jose, CA

37d•Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. AMD's Adaptive and Embedded Computing Group (AECG) is looking for a SoC Architect to join the team in defining the next generation of Adaptive and Embedded SoCs. You will drive novel SoC architecture solutions across a wide range of applications, including Embedded Computing, AI/ML, Data Center, Communications, Automotive, and Aerospace, in close collaboration with customers, partners, product planning, SoC and IP architects, and design & verification teams. As a SoC Architect you will help drive new architecture initiatives that leverage the state-of-the-art PCIe, CXL, UAL, and Confidential Compute technologies and standards. You will exercise your technical expertise and excellent communication skills to collaborate with design and product planning with an eye towards delivering innovative and highly competitive adaptive accelerators and embedded computing solutions.

Requirements

Strong technical background architecting SoC and I/O subsystems involving PCIe and PCIe-DMA engines.
Strong technical knowledge of the PCIe protocol specifications, and how mandatory and optional protocol features are leveraged in PCIe devices.
Domain expertise in embedded computing, aerospace & defense, data-center, networking, or automotive industries.
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPUs.
Knowledge of bridging and ordering rule enforcement between on-chip protocols such as AXI, and off-chip protocols such as PCIe desired.
BS/MS/PhD in electrical or computer engineering or related field.

Nice To Haves

Knowledge of ARM Processors and AXI Interconnects desired.
Knowledge of FPGA and AI/ML Accelerators desired.
Knowledge of boot, security, debug, telemetry and RAS desired.

Responsibilities

Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over PCIe, UAL or CXL.
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric.
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors.
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets.
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and external CPUs.
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase.