SoC Power Architect (Principal Engineer)

Samsung Electronics • Austin, TX

66d • $221,700 - $364,800

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Requirements

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a Ph.D.
• Deep experience in power modeling and analysis for complex semiconductor designs, with silicon power measurement expertise.
• Deep understanding of digital design concepts, dynamic and leakage power tradeoff.
• Strong understanding of mobile chip architecture and design concepts, including mobile scenarios, DVFS sequences, and PMIC operation.
• Strong proficiency in programming languages like Python, C++ for power modeling and analysis.
• Solid understanding of memory subsystems, including interconnect, last-level cache, coherency, and memory controllers (DDR, LPDDR, or HBM), along with DRAM power understanding.
• Effective attention to details, with the ability to multitask in a fast-paced, dynamic environment.
• Excellent analytical and problem-solving skills, with the ability to influence decisions using a data-driven approach.
• Excellent communication and collaboration skills, with the ability to navigate ambiguity in a global team environment.

Responsibilities

• Lead and contribute hands-on to the design and validation of power models for Samsung’s next-generation semiconductor designs.
• Accurately predict power consumption, optimize energy efficiency, and ensure the success of cutting-edge integrated circuits.
• Develop accurate power models across multiple levels of design abstraction, from RTL to gate level.
• Engage closely with coherent interconnect, memory controller, and last level cache (LLC) design specifications.
• Validate and refine models through simulation and real-world power measurements.
• Analyze results to uncover power-saving opportunities and guide design teams with data-driven recommendations.
• Collaborate with global teams, including architects, micro-architects, and physical design.
• Define power-saving microarchitectural features and integrate models seamlessly into the design flow.
• Mentor engineers, foster ownership, promote open communication, and continuously learn and experiment with emerging power modeling techniques.

Benefits

• Medical, dental, vision, life insurance
• 401(k)
• Onsite lunch
• Employee purchase program
• Tuition assistance (after 6 months)
• Paid time off
• Student loan program
• Wellness incentives
• MBO bonus compensation based on performance
• Eligibility for long term incentive plan and relocation

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees