SoC Full Chip DV Engineer

Apple • Cupertino, CA

159d

About The Position

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new insights have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what we'll could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology, and we'd love to have you join us.

Requirements

• Minimum of BS + 0 years relevant industry experience.

Nice To Haves

• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
• Knowledge of Verilog/SystemVerilog, digital simulation and debug.
• Knowledge of computer architecture and digital design fundamentals.
• Ability to work independently to deliver the project goals.
• Exposure to UVM is desired.
• Experience with C/C++, assembly is a plus.
• Experience with perl, python or similar scripting language.
• Excellent interpersonal skills and the dream to take on diverse challenges.

Responsibilities

• Ensure the quality of the SOC or an IP or subsystem.
• Review design and architecture specifications.
• Work closely with design & micro-architecture teams.
• Understand the functional & performance goals of the design.
• Develop test plans, tests & coverage plans.
• Define next generation verification methodology & test benches.
• Communicate and collaborate with design, architecture and software teams.
• Understand use cases and corner conditions to drive test cases.
• Run and triage regressions.
• Track bugs and analyze coverage to achieve top results.

What This Job Offers

• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees