SoC Design Verification Engineer

Intel-posted 11 months ago
$121,050 - $170,890/Yr
Full-time • Entry Level
Hybrid • Austin, TX
5,001-10,000 employees
Computer and Electronic Product Manufacturing
Resume
Match Score
Upload and Match ResumeTrack Jobs with Teal

Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. In this role you will be part of the XEG design team, working on next-generation Xeon server product SOCs and IPs.

  • Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
  • Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
  • Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
  • Replicates, root causes, and debugs issues in the pre-silicon environment.
  • Finds and implements corrective measures to resolve failing tests.
  • Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
  • Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
  • Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
  • Maintains and improves existing functional verification infrastructure and methodology.
  • Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
  • Strong debug skills and self-reliance in taking an issue to closure with internal and external partners.
  • Takes ownership of assigned tasks.
  • Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market.
  • Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 2+ years of technical experience.
  • Related technical experience should be in/with Silicon Design and/or Validation/Verification.
  • Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
  • Proficiency in UVM/SV constrained-random coverage based design verification.
  • OVM/UVM, System Verilog, constrained random verification methodologies.
  • The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
  • Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
  • UVM/SV Verification IP architecture, development and validation experience.
  • Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer.
  • Experience with one or more scripting languages to facilitate automation.
  • Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.
  • Competitive pay
  • Stock options
  • Bonuses
  • Health benefits
  • Retirement plans
  • Vacation
Track Jobs with Teal

Job Search Resources

•
Resume Builder
•
Resume Examples
•
Cover Letter Examples

Tools

Career Hubs

Guides

Company

© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service