SoC Design for testing Engineer, Google Cloud

Google-posted 3 months ago
$156,000 - $229,000/Yr
Full-time
Sunnyvale, CA
5,001-10,000 employees
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In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a DFT Engineer you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly complex digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost. The AI and Infrastructure team works on the world's toughest problems, redefining what's possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. We're at the center of amazing work at Google by being the "flywheel" that enables our advanced AI models, delivers computing power across global services, and offers platforms that developers use to build services. In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.

  • Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
  • Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
  • Develop diagnostic databases, software and hardware for logic and memory fail debug.
  • Design and Implement System Level Test strategy.
  • Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT Compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for complex IP blocks.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience in DFT architecture, implementation, and verification for SoCs.
  • Experience in silicon bring-up, debug, or validation of DFT features.
  • Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 10 years of experience in DFT architecture, implementation, and verification for SoCs.
  • Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
  • Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
  • Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
  • Knowledge of Test Standards (e.g., IEEE 1149.1, 1687) and Test Data Formats (e.g., BSDL, STIL).
  • The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits.
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