SoC Design for Test Engineer

Advanced Micro Devices-posted 5 months ago
Full-time • Entry Level
Hybrid • Boxborough, MA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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As a Design-for-Testability (DFT) Engineer at AMD, you will own the full DFT lifecycle-from specification definition through post-silicon bring-up-to ensure robust and efficient test solutions. You will collaborate closely with Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers, and Program Management to deliver successful and timely project outcomes.

  • Implement and verify DFT and Design-for-Debug (DFD) architectures and features.
  • Insert Scan, JTAG, and Boundary Scan chains; generate ATPG patterns.
  • Generate, implement, and verify Memory Built-In Self-Test (BIST) logic.
  • Apply low power DFT techniques to designs.
  • Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
  • Analyze test coverage and work on reducing test costs.
  • Provide post-silicon support to ensure successful bring-up and improve yield learning.
  • Strong understanding of Design For Test methodologies and DFT verification (e.g., IEEE1500, JTAG 1149.x, scan, memory BIST).
  • Experience with Tessent TestKompress and Silicon Scan Network (SSN).
  • Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
  • Exposure to static timing analysis and timing closure processes.
  • Experience in pre-silicon test planning, validation, and engagement with design teams.
  • Skilled in characterization and debugging of scan/ATPG tests in new silicon designs and process technologies.
  • Expertise in optimizing test flows for quality enhancement and cost reduction.
  • Ability to analyze part failures to improve test coverage and yield.
  • Experience analyzing characterization data across process, voltage, and temperature (PVT) corners.
  • Excellent communication skills and ability to work effectively in a global team environment.
  • Knowledge of low power design concepts such as clock gating and power gating is a plus.
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