As part of Design Enablement's Library and Technology team you will join a highly motivated group of top-notch engineers solving challenging technical problems in physical design pathfinding. Your responsibilities will include, but are not limited to: Perform block PPA with emphasis on synthesis, place, and route on latest internal/external core/graphics/soc designs and target for ambitious power, performance, and area. Work with process team to co-define next generation technology node from ground up and push Moore's law to next level. Explore standard-cell architectures together with library team and provide guidance to library optimization and choice through block PPA. Explore memory options for next technology nodes and provide block PPA impact Co-optimize TFM with EDA tool vendors (primarily Synopsys and Cadence) to boost block PPA and deliver world-class process offering. Develop in-house physical design machine learning capability to explore design solution space and push block PPA as well as provide guidance to process technology optimization direction. Work intensively with product teams to provide block PPA guidance as well as TFM recommendations. Design delivery: Bring designs from block PPA and realize in silicon through test-chip and demonstrate world leading silicon.