ARM-posted 3 months ago
$221,127 - $299,172/Yr
Hybrid • Chandler, AZ
5,001-10,000 employees
Professional, Scientific, and Technical Services

We are seeking a skilled SoC (System-on-Chip) CoreSight Debug Architect to join our dynamic team. In this role, you will be responsible for architecting the SoC level CoreSight debug architecture across a portfolio of SoCs covering multiple market segments, ensuring the efficient and effective resolution of complex issues throughout the development lifecycle. You will also develop the micro-architecture and work with design and verification engineers to realize your solutions as well as multi-functional teams to identify, prioritize, and resolve in-silicon issues, playing a pivotal role in delivering high-quality products to partners. This opportunity is available across the following US locations; San Diego, Chandler, San Jose and Austin.

  • Develop and maintain the SoC CoreSight debug strategy and roadmap, collaborating with hardware and software teams to develop debug requirements
  • Design and implement innovative and efficient debug architectures and tooling for complex devices covering software tracing/debug as well as hardware debug.
  • Drive continuous improvement initiatives to streamline debug processes and shorten time to resolve issues (Debug Throughput Time)
  • Keep abreast of industry trends and ensure debug capabilities are keeping pace with future architectures, features, and constructions
  • Interact directly with partners to understand their needs and challenges
  • Proven experience (15+ years) in SoC architecture/design and (5+ years) in SoC debug architecture design, implementation and deploying debug techniques for digital and mixed-signal functionality in a post-Si production environment.
  • Must have expertise with CoreSight Design for Debug (DFD) techniques such as observability points, trace buffers, and error detection mechanisms
  • Must have proficiency with ARM-specific CoreSight debug solutions, Debug Access Ports (DAPs), Embedded Trace Macrocells (ETMs), System Trace Macrocells (STMs), Embedded Logic Analyzer (ELA), Trigger (CTI, CTM)
  • Understanding of on-chip debug network for Configuration and data transport along with the ROM tables and memory maps
  • Strong background in digital design, RTL coding (Verilog/VHDL), and ASIC/FPGA debug methodologies
  • Strong leadership and interpersonal skills with the ability to effectively communicate and collaborate with multi-functional teams
  • Competitive salary range of $221,127-$299,172 per year
  • Hybrid working environment that supports flexibility
  • Commitment to equal opportunities and a diverse workplace
  • Support for accommodations during the recruitment process
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