SMTS Analog/Mixed-Signal Design Engineer

Rambus-posted 7 months ago
$112,000 - $208,000/Yr
Full-time • Mid Level
San Jose, CA
Professional, Scientific, and Technical Services
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Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Analog/Mixed-Signal Design Engineer to join our Bufferchip Design team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.

  • Ownership of Analog/Mixed designs at chip and/or block level
  • Implement optimal circuit architectures to achieve competitive product specifications
  • Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, ADC, DAC, LDO, PLL, DLL, PI circuits)
  • Create floorplan and work with layout team to demonstrate post extraction performance
  • Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow
  • Work with the Lab/System team for test plan, silicon bring up and characterization
  • Create behavior model for verification simulations
  • MS EE and 2+ years or PhD EE in CMOS analog/mixed-signal circuit design
  • Prior work experience or research thesis in at least one of the following circuits: Transmitter, Receiver (with CTLE, DFE), PLL, DLL, PI, clock distribution
  • Good knowledge of design principles for practical design tradeoffs
  • Fundamental knowledge of basic building blocks like bias, op-amps
  • Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE is highly desirable
  • Prior experience or course work in FinFET process and digitally assisted design is desirable
  • Experience in modeling with matlab, Verilog-A, verilog is desirable
  • Experience working in leading R D and future technology development projects is desirable
  • Good written & verbal communication skills
  • Strong commitment and ability to work in cross functional and globally dispersed teams
  • Experience in designing memory interfaces such as DDR 4/5 or serial links such as PCIE
  • Prior experience or course work in FinFET process and digitally assisted design
  • Experience in modeling with matlab, Verilog-A, verilog
  • Experience working in leading R D and future technology development projects
  • Competitive compensation package including base salary, bonus, equity
  • Matching 401(k)
  • Employee stock purchase plan
  • Comprehensive medical and dental benefits
  • Time-off program
  • Gym membership
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