Silicon Packaging Layout Engineer

Celestial AI • Santa Clara, CA

33d • $165,000 - $215,000 • Onsite

About The Position

We are seeking an experienced Silicon Packaging Layout Engineer with expertise in heterogeneous integration. The ideal candidate will have a strong background in semiconductor packaging design to drive Celestial AI's Photonic Fabric Package solutions. This role requires cross-functional design collaboration with multiple engineering groups, such as Packaging, ASIC, AMS, Photonics, and external partners to ensure design for manufacturing, assembly, reliability, and cost.

Requirements

• Education: BS in EE/ECE/MSE/ME/ChemE or related disciplines.
• Experience: 4 years of experience in silicon interposer and RDL designs for heterogeneous architectures.
• Technical Expertise:
• Experience working with design tools such as Cadence Virtuoso and Klayout.
• Familiarity with AutoCAD tools and file formats.
• Layout experience for various 2.5D/3D packaging technologies including InFO, CoWoS, FoCoS and EMIB.
• Familiarity with cross-functional packaging areas: Si floor plan, package, assembly design rules, BOM, enabling material/process technologies, thermal, mechanical, Signal/Power Integrity, design for manufacturing, assembly, reliability, and cost.
• Foundry and OSAT Engagement:
• Experience working with wafer foundries to meet design for manufacturing, yield, and reliability.
• Experience working with OSATs to meet assembly requirements.
• Industry Knowledge: Familiarity with latest advanced packaging architectures.
• Soft Skills: Strong analytical, problem-solving, cross-functional collaboration, project management, and technical presentation skills.

Nice To Haves

• Experience in silicon layout for heterogeneous integration, fan-out packaging, chiplet architectures - co-design, physical layout, and netlist management.
• Experience with fab and assembly design rules.
• Experience in foundry and OSAT assembly engagement to meet manufacturing and assembly requirements.
• Familiarity with photonics packaging is a plus but not necessary.

Responsibilities

• 2.5D and 3D Design Planning and Execution:
• Support Silicon interposer and RDL based design planning and execution for advanced packaging architectures.
• Support bumpmap and test collateral release for test vehicle and product designs.
• Netlist management for heterogeneous chiplet assemblies using latest EDA solutions.
• Layout Expertise:
• Support all aspects of silicon layout based on I/O, SI-PI and form factor requirements, including routing, design for reliability, thermal, mechanical, manufacturability, bumping, substrate, material selection, assembly, and support for testing.
• Support cross-functional silicon layout needs.
• Fab and OSAT Engagement:
• Support activities related to silicon manufacturing such as fab design reviews and tape-out aligned with OSAT requirements.
• Actively support test vehicle definition and design for assembly test vehicles.

Benefits

• We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Publishing Industries
• Number of Employees: 101-250 employees