Silicon Microarchitecture Engineer

DeepMind • Mountain View, CA

13h

About The Position

Artificial Intelligence could be one of humanity’s most useful inventions. At Google DeepMind, we’re a team of scientists, engineers, machine learning experts and more, working together to advance the state of the art in artificial intelligence. We use our technologies for widespread public benefit and scientific discovery, and collaborate with others on critical challenges, ensuring safety and ethics are the highest priority. About Us At Google DeepMind, we've built a unique culture and work environment where long-term ambitious research can flourish. We are seeking a highly motivated Hardware Engineer to join our team and contribute to development of groundbreaking silicon for machine learning acceleration. The Role Key responsibilities: Work in a fast and interdisciplinary team bringing together experts from Machine Learning, Hardware, Programming Languages and Systems High performance machine learning accelerator architecture, micro-architecture and RTL design. Selection and integration of in-house and third party IP. Exploration of various trade-offs of future architecture designs in terms of performance, power, energy, and area. Participate in the system architecture definition and evaluation. Collaboration with simulation and PD teams to maintain up to date cost functions for architecture evaluation. Coordinate the chip design collaboration across the teams. Collaboration with the design automation teams and provide steering and guidance for tool development. About You We are seeking a talented and highly motivated hardware engineer to join our GenAI technical infrastructure research hardware team. You will have the opportunity to partake into cutting-edge architecture exploration that will shape the future of machine learning acceleration. In order to set you up for success as a Software Engineer at Google DeepMind, we look for the following skills and experience:

Requirements

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 7+ years of experience in RTL design in Verilog/System Verilog.
• 5+ years of experience in micro-architecture definition.
• 3+ years of experience in RTL design verification.
• Experience with high performance compute IPs (e.g., GPUs, DSPs, or machine learning accelerators).
• Experience in evaluating trade-offs such as speed, performance, power, area.
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Hands-on knowledge of basic hardware requirements and building blocks of ML accelerators - custom number formats, matrix multiply units, vector and elementwise computation etc.

Nice To Haves

• Working experience developing with C++ & Python.
• Physical Design background or hands on experience.
• Design Verification background or hands on experience.
• Knowledge/understanding of high level synthesis.
• Working knowledge of transformer-based large language models.
• Knowledge of high performance and low power architectures for ML acceleration.
• Knowledge of processor core SoC integration

Responsibilities

• Work in a fast and interdisciplinary team bringing together experts from Machine Learning, Hardware, Programming Languages and Systems
• High performance machine learning accelerator architecture, micro-architecture and RTL design.
• Selection and integration of in-house and third party IP.
• Exploration of various trade-offs of future architecture designs in terms of performance, power, energy, and area.
• Participate in the system architecture definition and evaluation.
• Collaboration with simulation and PD teams to maintain up to date cost functions for architecture evaluation.
• Coordinate the chip design collaboration across the teams.
• Collaboration with the design automation teams and provide steering and guidance for tool development.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees