Signoff Methodology Engineer - New College Grad 2026

NVIDIA•Us, CA

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, informative analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence! We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an ideal role.

Requirements

MS or PhD in Electrical or Computer Engineering (or equivalent experience).
Good understanding of modeling circuits for sign-off.
Knowledge of extraction, device physics, STA methodology and EDA tools limitations.
Shown understanding of mathematics/physics fundamentals of electrical design.
Understanding of 3DIC, stacking, packing, self-heating and its impact on timing/STA closure.
Background with crosstalk, electro-migration, noise, OCV, timing margins.
Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.

Nice To Haves

Shown interpersonal skills across multiple teams is a plus.

Responsibilities

Improve and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation.
Develop custom flows for validating QoR of ETM models, both of std cells and custom IPs.
Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging, self-heating, thermal impact, IR drop etc.
Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
Work on various aspects of STA, constraints, timing and power optimization.