Signal Integrity Hardware Engineer

Pure Storage•Santa Clara, CA

6h•Onsite

About The Position

We’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry. Pure builds the industry’s most innovative, high-performance, energy-efficient and TCO-optimised storage solution. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. We are seeking a highly motivated Hardware Signal Integrity (SI) Engineer for Pure’s Datastore team. In this role, you will own high-speed signal integrity analysis, simulation, and measurement for enterprise SSD platforms.

Requirements

5+ years of experience in Signal Integrity engineering for high-speed systems.
B.S. Electrical or Computer Engineering (M.S. is a plus).
Strong SI simulation experience, must-have for PCIe and nice to have for NAND and DDR, for channel analysis, eye simulations, jitter, margin, etc.
Hands-on TDR and S-parameter measurement experience
Strong understanding of PCB design from an SI perspective, including materials, stackups, and via structures.
Deep experience with Simbeor (3D-EM extraction and simulation).
Ability to understand system design tradeoffs (SI, Performance, Mechanical, Thermal, Power).
Detail oriented, analytical, process savvy, and customer focused yet flexible and adaptable to business needs
Highly self-motivated with the ability to work autonomously in a fast-paced, technical development environment
Experience working in and leading cross-functional team
High level of teamwork and collaboration skills

Nice To Haves

Familiarity w/ SSD design w/ different form factors is a plus
Experience with SSD standard and compliance testing, ie PCI-SIG, NVMe, etc. is a plus

Responsibilities

Own signal integrity analysis for SSD hardware from architecture through production.
Drive board-level SI decisions, including: PCB material selection, via structures, loss tradeoffs, stackup definition and channel optimization.
Perform SI simulations including: Insertion loss (IL), return loss (RL), crosstalk, TDR / impedance profiles.
Lead TDR and S-parameter measurements, including: measurement setup, Calibration and de-embedding.
Perform 3D-EM extraction and simulation for vias, connectors, and complex channel structures.
Correlate simulation results with lab measurements to refine models and design assumptions.
Use and customize IBIS and IBIS-AMI models for PCIe, NAND and DDR channel analysis.
High speed signal eye diagram and margin analysis.
Support debug activities where SI is a contributing factor.
Collaborate cross-functionally with PCB design, system, firmware, mechanical, and test teams to ensure robust SI solutions.
Document SI design guidelines and best practices to enable scalable, repeatable designs.
Provide technical leadership and mentorship to junior engineers.
We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.