SerDes Validation Senior Staff Engineer

Marvell Technology•Santa Clara, CA

About The Position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell post silicon validation group designs and develops test platforms for validating enterprise, cloud, AI, and carrier architectures including multi-core Arm-based Network processors. The electrical characterization team is a post silicon validation sub-group focused on the debug and characterization of SerDes interfaces on the processor. The SerDes interface use NRZ and PAM4 signaling for Ethernet, PCIe and Die-to-Die interfaces. Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over process voltage and temperature (PVT) extremes to determine silicon viability for volume production. What You Can Expect Marvell is seeking Senior Staff Validation Engineer in the Custom Compute and Storage Business Group to validate Ethernet, PCIe and other high-speed interfaces in post-silicon environment. It encompasses the full development cycle of Marvell state-of-the-art SerDes development from IP stage to productization into customer application. It involves all aspects of SerDes engineering including circuitries, DSP algorithm and initialization for electrical performance and compliance. As a high speed SerDes validation Engineer, you will focus on the validation of Ethernet/PCIe/Die-to-Die interface as well as supporting the debug and functional tests of the PHY. You’ll have an opportunity to work on the latest Ethernet 224G, PCIe Gen6/7 technology and product development, along with other advanced high-speed SerDes. Complete ownership of high speed SerDes validation in post-silicon environment. Document, execute and report overall PHY validation for Marvell custom silicon devices. Perform lab-based silicon bring-up and SerDes engineering focused on Ethernet/PCIe/D2D Physical layer functionality. Participate in collaborative discussions to drive resolution for technical issues. Troubleshoot failing tests with diagnostics, hardware analyzers and software tools. Work with cross-functional teams to debug any post-silicon and/or customer issues related to SerDes PHY.

Requirements

Bachelor’s degree in Electrical Engineering or related fields and 5-7 years of related professional experience OR Master’s degree in Electrical Engineering or related fields with 3-5 years of experience.
3+ years of experience with high-speed IO testing, debugging and validation
In depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer etc.).
Strong understanding of high-speed SerDes, equalization technique and SerDes links and channels.
Working knowledge of Ethernet/PCIe interface and characterization.
Experience with Python, or other programming language.
Critical thinking and problem-solving attitude and ownership of the group’s results.
Excellent verbal and written communication skills.

Nice To Haves

Knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
Knowledge of board design, board schematics and board layout, and signal integrity is a plus.

Responsibilities

Complete ownership of high speed SerDes validation in post-silicon environment.
Document, execute and report overall PHY validation for Marvell custom silicon devices.
Perform lab-based silicon bring-up and SerDes engineering focused on Ethernet/PCIe/D2D Physical layer functionality.
Participate in collaborative discussions to drive resolution for technical issues.
Troubleshoot failing tests with diagnostics, hardware analyzers and software tools.
Work with cross-functional teams to debug any post-silicon and/or customer issues related to SerDes PHY.