Draper Laboratory-posted 10 months ago
Full-time • Mid Level
Cambridge, MA
1,001-5,000 employees
Professional, Scientific, and Technical Services
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Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.
