About The Position

We are seeking a Senior Technologist, Technology Development Engineering to join our Advanced Technology Group team in Milpitas, United States. In this pivotal role, you will lead cutting-edge technology development projects, define future design architectures, define future CMOS technologies and help drive Design Technology Co-Optimization efforts working together with both CMOS and Design teams.

Requirements

  • Requires PhD or MS in Electrical Engineering or equivalent with 10 or more years of relevant experience
  • A strong device background and experience with evaluating new process technologies for use in design is preferred
  • Self-motivated and self-directed, however, must have demonstrated ability to work well with people
  • A proven desire to work as a team member, both on the same team and outside of the team
  • Excellent communication (written and verbal) and interpersonal skills
  • Ph.D. or Master's degree in Electrical Engineering, Materials Science, or a related field
  • 8-10 years of experience in circuit design
  • Proficient in PPA analysis using standard PDK kits
  • 3+ yrs Experience with DTCO optimization for advanced CMOS nodes
  • Familiar with advance CMOS technologies, spice models, design rules and PDK kits
  • Advanced knowledge of semiconductor technology and process integration

Nice To Haves

  • Knowledge and/or experience in memory design is a big advantage
  • Proven track record of successful technology development projects
  • Expertise in data analysis and statistical tools for process optimization
  • Strong problem-solving skills and ability to tackle complex technical challenges
  • Excellent communication and leadership abilities to guide cross-functional teams
  • Proficiency in presenting technical information to both technical and non-technical audiences
  • Well versed in industry standard circuit simulation tools

Responsibilities

  • Collaborate on Design Technology Co-Optimization (DTCO) to align circuit design with advanced process technologies for optimal performance and efficiency
  • Define and validate CMOS technologies, design rules and perform PPA (performance, power and area) analysis
  • Designing, optimizing, verifying, and debugging transistor-level circuits for emerging 3D non-volatile memory
  • Design and analysis of memory core circuits such as Row/Column drivers, decoder, sense amplifier, etc.
  • Mixed-signal/analog design to implement core operation supporting circuit design
  • Validate design performance and functionalities by running block and chip-level simulations using industry-standard IC tools such as Cadence design environment, HSPICE/FINESIM, UNIX
  • Supervise layout work, support verification, and silicon bring-up throughout the design cycle
  • Conceive new concepts and approaches in memory core design, architecture, and operation algorithm for best-performing NAND device
  • Mentor and guide junior engineers, fostering a culture of technical excellence

Benefits

  • We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan.

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What This Job Offers

Job Type

Full-time

Career Level

Senior

Education Level

Ph.D. or professional degree

Number of Employees

5,001-10,000 employees

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