Senior Technical Staff Engineer - Design for Test

Microchip • San Jose, CA

72d • $88,000 - $232,000

About The Position

The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture, ASIC design, verification, physical implementation, and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape-out, as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).

Requirements

• 15+ years of DFT engineering experience through DFT pre and post silicon cycles.
• Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes.
• Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF/TDF/PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC/FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test.
• Familiar with DFT verification, silicon debug, memory and scan diagnostics.
• Experience in PHY, high-speed IO, digital communication and functional test development.
• Good understanding of Verilog, synthesis, physical implementation and STA.
• Good understanding of verification methodology.

Nice To Haves

• Knowledge of FPGA design flow is a plus.
• Knowledge of embedded design and firmware methodology is a plus.
• Understanding Arm or RISC IP’s, high speed interfaces such as PAM4 SerDes, DDR4/5, etc. is a plus.
• Experience in leading multiple FPGA/SoC projects.

Responsibilities

• Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level. Define, implement and validate DFT features at the FPGA full chip and sub-systems level.
• Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test and quantifying full chip test coverage.
• Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.
• Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality.
• Work with Test and Product engineers to support development of firmware targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities.
• Communicate project status and progress to chip lead and engineering management.

Benefits

• Competitive base pay.
• Restricted stock units.
• Quarterly bonus payments.
• Health benefits that begin day one.
• Retirement savings plans.
• Industry leading ESPP program with a 2 year look back feature.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees