Senior Technical Staff Engineer - Architect (DFT Lead)

Microchip-posted 4 days ago

Full-time • Mid Level

Austin, TX

5,001-10,000 employees

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Microchip Technology Inc. has a Senior Technical Staff Engineer - Architect (DFT Lead) opening based in Austin, TX and Chandler, AZ . The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture, ASIC design, verification, physical implementation, and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape-out, as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).

Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level.
Define, implement and validate DFT features at the FPGA full chip and sub-systems level
Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test and quantifying full chip test coverage
Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow
Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality
Work with Test and Product engineers to support development of firmware targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities
Communicate project status and progress to chip lead and engineering management

Bachelors or Masters in engineering field
15+ years of DFT engineering experience through DFT pre and post silicon cycles
Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes
Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF/TDF/PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC/FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test
Familiar with DFT verification, silicon debug, memory and scan diagnostics
Experience in PHY, high-speed IO, digital communication and functional test development
Good understanding of Verilog, synthesis, physical implementation and STA
Good understanding of verification methodology

Knowledge of FPGA design flow
Knowledge of embedded design and firmware methodology
Understanding Arm or RISC IP’s, high speed interfaces such as PAM4 SerDes, DDR4/5, etc.
Experience in leading multiple FPGA/SoC projects.

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