Senior Technical Leader, EPYC SOC Architecture

Advanced Micro Devices, Inc

2d•Hybrid

About The Position

As a senior technical leader in AMD’s EPYC Datacenter SOC Architecture team, the EPYC Server SOC Architect will play a pivotal role in shaping the future of AMD’s datacenter CPU roadmap. This position offers a unique opportunity to combine system-level architectural innovation and SOC execution capability with strategic customer and business alignment to influence the direction of modern computing platforms at hyperscale. You will also lead definition, specification, and balance ability to deliver advanced EPYC CPU and SOC capabilities—spanning compute, memory, IO, security, virtualization, and power optimization—while engaging directly with customers, ecosystem partners, and internal stakeholders. Your work will help drive AMD’s competitiveness across cloud, enterprise, AI/ML, and HPC markets. You are a technical leader with a track record of delivering industry-defining architectures. You thrive at the intersection of technology, business, and customer engagement, and excel at connecting long-term strategic thinking with real-world execution. You understand not only how to build advanced CPUs, but why those features matter—to customers, to markets, and to the business. You can lead and facilitate detailed technical definitions of capabilities by yourself and by other engineering and technical leaders across logical design, physical design, and design verification and validation. You are naturally collaborative, deeply curious, and comfortable influencing across a matrixed organization. You believe in leading through inclusion, mentorship, and partnership—and in bringing out the best in cross-functional teams.

Requirements

Demonstrated leadership in the architecture and delivery of high-performance CPUs or SOCs.
Deep technical expertise in one or more of the following: CPU microarchitecture, performance analysis/architecture, SOC system design and chiplet architecture, memory hierarchy, virtualization, interconnect, or power management.
Experience engaging directly with hyperscalers, OEMs, or other strategic partners on product planning or workload optimization.
Strong understanding of datacenter workload trends including cloud-native computing, AI/ML head-node requirements, and infrastructure scalability.
Ability to mentor, influence, and align diverse technical teams across geographies and domains.

Nice To Haves

Track record of thought leadership through publications, patents, or industry contributions is a plus.
Familiarity with AMD architecture and ecosystem a plus but not required.

Responsibilities

Lead the architecture and delivery of EPYC CPUs or SOC-level capabilities from definition through high-volume production.
Act as a trusted technical partner to key customers, translating workload trends, deployment challenges, and operational priorities into actionable architectural strategies.
Drive long-range planning and alignment across business units for datacenter, AI training/inference, and HPC product lines.
Shape and assess platform-level trade-offs to improve Total Cost of Ownership (TCO) for EPYC-based solutions.
Represent AMD in strategic industry engagements, standards discussions, and high-value customer engagements as a thought leader.
Define and evangelize advanced features in memory architecture (DDR, LPDDR, CXL), on-chip coherence, chiplet integration, IO subsystems, and AI/ML-ready CPU design.
Collaborate deeply with internal teams—RTL, physical design, firmware/software, performance, and validation—to ensure feature definition and design closure, along with product competitiveness.
Own overall program feature set closure and reconciliation across a matrixed organization of technical and product leads
Champion a culture of technical excellence, inclusivity, and cross-functional transparency across global teams.