Senior Staff System & Modeling Engineer – Wireline Communications

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Senior Staff Engineer with Marvell, you'll be part of the Central Engineering organization, providing the most advanced and key analog IPs to all businesses within Marvell. You’ll be part of a key analog team that makes an outsized impact not only for the organization but also to the technological arc of innovation for future generations of Marvell's high-speed wireline and optical products. In this role, you will contribute to the architecture, modeling and verification of high-speed wireline communication systems, focusing on system-level architecture, DSP, and behavioral modeling of analog and mixed-signal blocks. Your work will enable accurate simulations, validate architectural decisions, and support functional verification for next-generation wireline interconnect technologies.

Requirements

PhD or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5-10+ years of experience in system modeling and analog abstraction for wireline communication systems.
Solid knowledge of DSP techniques for ultra-high speed wireline systems
Solid knowledge of equalization techniques used in wireline channels, including Continuous-Time Linear Equalizers (CTLE), Feed-Forward Equalizers (FFE), and Decision Feedback Equalizers (DFE).
Very good understanding of analog and mixed-signal circuit behavior and abstraction techniques.
Experience with SerDes standards such as PCI Express (PCIe), Universal Chiplet Interconnect Express (UCIe), or other high-speed interconnect protocols.
Excellent problem-solving and analytical skills.
Strong communication and collaboration abilities.
Strong proficiency in System Verilog, Verilog, MATLAB, Simulink, C/C++, Python, and scripting tools.

Responsibilities

Architect and model end-to-end wireline communication systems using MATLAB, Simulink, SystemVerilog, C/C++, and Python to support modeling, verification, and architectural exploration.
Devise novel DSP techniques to push the envelope of performance for ultra-high-speed wireline systems
Develop models that accurately capture performance, interface characteristics, and key non-idealities or impairments (e.g., bandwidth limitations, jitter, noise, distortion) of key analog blocks.
Collaborate closely with other system architects to explore design trade-offs, validate architectural assumptions, and refine system-level specifications.
Model analog and mixed-signal circuit blocks (e.g., CTLEs, ADCs, PLLs, TX/RX front-ends) using SystemVerilog or other HDLs to support functional design verification and system-level integration.
Work with analog designers and signal integrity engineers to ensure model fidelity and alignment with physical implementation.
Support lab testing and debugging of prototype systems and silicon bring-up.
Mentor junior engineers and provide technical leadership across modeling and verification efforts.
Author technical documentation, modeling guidelines, and contribute to customer-facing deliverables.