Senior Staff Physical Design Manager

Marvell•Santa Clara, CA

40d•Onsite

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Marvell Physical Design team is located in our Santa Clara, CA office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology.

Requirements

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
Must have a background in ASIC or SOC development
Physical design knowledge, from netlist handoff to GDS tape-out including floor planning, place and route, clock tree synthesis, timing closure and physical verification
Must be able to handle a wide variety of projects and technical challenges
Diligent, detail-oriented, and able to handle assignments with minimal supervision
The successful candidate will have excellent written and oral communications skills, and ability to collaborate and be effective in fast-paced environment
Self-driven individual and with ability to partner with world-wide team

Nice To Haves

Minimum 2 years of experience leading projects within semiconductor product development or tape-out cycles. Proven track record of team mentorship for high performance.
Technical leadership of ASIC or SOC Netlist to GDS tape-out
Experience as either top-level physical design lead, STA chip Lead or chip DFT lead
Project management experience of ASIC or SOC
Customer interface experience
Experience working with a distributed team

Responsibilities

Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
Assist in planning and designating project resources, monitor progress, and keep stakeholders informed the entire way
Partner with other ASIC design teams to ensure project success
Possibility of being management interface to ASIC customers
Lead recruiting efforts at local universities and hiring of experienced engineers