Senior Staff GPU Design Verification Engineer- Power

Qualcomm•San Diego, CA

About The Position

Qualcomm CDMA Technologies (QCT) is the world leader in wireless ICs powering the majority of 5G devices and is the largest fabless semiconductor in the world. QCT's Digital ASIC design team delivers cutting edge hardware and software products that power the user’s experience and graphics content of the most advanced mobile devices on the market. Responsibilities will include Work with Architecture and Design team to understand the low power design features and create verification plan Develop test plan documents for the design features and get them reviewed with design team Develop verification components, testbench for low power verification and integrate third party VIPs/UVCs as required Create constraint random verification environment using System Verilog, UVM Follow company defined verification methodologies Perform Power Aware Verification in a random verification environment with embedded firmware running on the design Regress and close the required Low Power coverage metrics to ensure high quality design Create portable test setup, verification components that can be reused across simulation, emulation platforms Perform failure debug involving hardware software co-debug Work with tool vendors and push the methodology to improve the verification flows. System level RTL simulation & design verification. Support SoC DV for their integration verification, chip bring up and post silicon debug.

Requirements

Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 6+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 5+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Nice To Haves

Bachelor’s degree in science, engineering, or closely related field
5+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification.
5+ years in Design validation/post-silicon debug.
5+ years of hands-on experience in developing verification components/UVCs, testbench for RTL verification
5+ years of hands on testbench bringup, integrating third party VIPs, digital design, verification, debugging, and waveform debug
3+ years of experience in UPF based Power Aware verification
3+ years of experience in Functional coverage model development and/or code coverage closure
MS degree in Electrical Engineering or equivalent; 8 years of practical experience
Power Aware Emulation verification experience
Hardware/Software Co-verification or embedded firmware verification experience is highly desirable
Worked on Low Power coverage metrics collection and coverage closure
Knowledge of GPU/CPU/DDR/Bus preferred
Scripting skills using Python
Formal verification experience (AND/OR) Low Power Formal Verification experience

Responsibilities

Work with Architecture and Design team to understand the low power design features and create verification plan
Develop test plan documents for the design features and get them reviewed with design team
Develop verification components, testbench for low power verification and integrate third party VIPs/UVCs as required
Create constraint random verification environment using System Verilog, UVM
Follow company defined verification methodologies
Perform Power Aware Verification in a random verification environment with embedded firmware running on the design
Regress and close the required Low Power coverage metrics to ensure high quality design
Create portable test setup, verification components that can be reused across simulation, emulation platforms
Perform failure debug involving hardware software co-debug
Work with tool vendors and push the methodology to improve the verification flows.
System level RTL simulation & design verification.
Support SoC DV for their integration verification, chip bring up and post silicon debug.