Senior Staff Engineer, Static Timing Analysis (STA) Engineer

Marvell Technology•Santa Clara, CA

1d•Onsite

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Design Center Engineering Physical Design team at Marvell in Santa Clara is seeking a Senior Staff Engineer, Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projects—from artificial intelligence and machine learning to advanced wired and wireless infrastructure—using the latest technology nodes.Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance, power, and area (PPA) goals. This role involves close collaboration with Physical Design, Design for Test (DFT), and other cross-functional teams across both local and global sites. What You Can Expect This role is based in Santa Clara, CA. Relocation will be required if you are not already in the area. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

Requirements

Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
8+ years experience in back-end physical design and verification.
Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues like N5/N3/N2.
Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure.
Expertise in full-chip & sub-hierarchy integration preferred
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in Perl, tcl and Python
Strong knowledge in static timing analysis (Primetime preferred) and SDC timing constraints
Understanding of digital logic and computer architecture
Knowledge of Verilog
Good communication skills and self-discipline contributing in a team environment

Nice To Haves

Experience with multi-voltage and low-power design techniques is a plus
Experience with Cadence Innovus is preferred

Responsibilities

Perform timing analysis and closure on complex partitions
Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner
Implement/support multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools
Work with RTL design teams to drive assembly and design closure
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation