Senior Staff Engineer- FPGA RTL Developer

Pivot + Edge•Dallas, TX

21d

About The Position

Macnica Americas, Inc. is the North American division of Macnica Fuji Electronics Holdings, Inc. a $10 billion technology solutions provider with a stronghold in semiconductor distribution. Macnica excels in customizing solutions to client requirements and leveraging skilled engineers to expedite product development without compromising outcomes for our clients. We are seeking a highly experienced Senior Staff FPGA RTL Engineer with over 10 years of hands-on development experience across both Intel (Altera) and AMD/Xilinx FPGA platforms. The ideal candidate possesses deep expertise in Verilog/SystemVerilog, complex SoC/FPGA architectures, and has a proven track record delivering high-performance, production-quality FPGA designs. Experience with Ethernet, SERDES, DDR, HDMI, and other high-speed interfaces is highly desirable. Candidates with backgrounds in video processing, Pro-AV, broadcast, imaging pipelines, or JPEG/MPEG compression technologies will be strongly preferred. This role also requires extensive lab experience, including debugging with oscilloscopes, logic analyzers, and FPGA-specific debug tools. You will work cross-functionally with hardware, software, and systems teams to architect, develop, verify, and optimize advanced FPGA-based solutions for demanding real-time applications.

Requirements

10+ years of experience developing complex RTL designs using Verilog/SystemVerilog.
Extensive hands-on experience with AMD/Xilinx (Vivado, Vitis, BDs, Zynq/Ultrascale+) and Intel/Altera (Quartus, Platform Designer/Qsys) FPGA toolchains.
Extensive, hands-on experience with AXI (AXI4, AXI-Lite, AXI-Stream) for high-performance and control-plane designs.
Extensive experience with Intel Avalon (Avalon-MM, Avalon-ST) on Qsys/Platform Designer systems.
Deep experience with PCI Express design and integration, including: – PCIe endpoints/RCs – DMA engines – High-bandwidth streaming or memory-mapped PCIe pipelines – Driver interaction and debug
Strong expertise with high-speed digital interfaces, such as Ethernet (1G/10G/25G+) MAC/PHY, SERDES/transceivers, DDR3/DDR4/DDR5, HDMI/SDI or other video PHYs.
Strong background with FPGA constraint setup, timing closure, clocking strategies, and CDC design practices.
Proficiency with RTL simulation, UVM or similar verification methodologies, and hardware debug tools.
Hands-on lab experience using oscilloscopes, logic analyzers, pattern generators, and FPGA debug instrumentation (ILA/SignalTap).
5+ years of experience with FPGA-based SoCs and embedded development in C/C++.
Familiarity with Linux-based development environments and scripting languages (Python, Tcl, bash).
B.S. or M.S. in: Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of hands-on FPGA/SoC design and development experience.

Nice To Haves

Experience with video, imaging, or compression pipelines (JPEG, MPEG, JPEG2000, JPEG XS, etc.) is a strong plus.
Knowledge of packet processing, video-over-IP, Pro-AV, broadcast, or imaging systems is a plus.

Responsibilities

Architect, design, and implement advanced RTL using Verilog and SystemVerilog for complex digital and SoC systems.
Lead FPGA development efforts across Intel/Altera and AMD/Xilinx platforms, including IP integration, timing closure, and system optimization.
Perform in-depth simulation, verification, linting, CDC analysis, and system-level validation.
Develop and integrate embedded C/C++ software for FPGA configuration, testing, and control.
Define and implement FPGA constraints, conduct static timing analysis, and optimize builds for performance, resource efficiency, and power.
Work hands-on in the lab with oscilloscopes, logic analyzers, protocol analyzers, and JTAG/ILA tools to debug and validate hardware.
Collaborate with firmware, software, and system architects to ensure seamless end-to-end integration.
Participate in design reviews, documentation, architecture discussions, and mentoring junior engineers.
Drive continuous improvement in development methodology, verification quality, and design robustness.