Senior Staff Engineer, Analog Layout

Marvell Technology • Santa Clara, CA

102d • $118,190 - $177,100

About The Position

Marvell is seeking a Senior Staff Analog Custom Layout Engineer to contribute to developing high-speed connectivity, broadband analog, and data transport products. The role involves designing and optimizing analog mixed-signal layouts such as high-speed ADCs, PLLs, bandgap voltage references, LDOs, high-speed I/O circuits, general I/Os, and ESD structures in deep sub-micron CMOS technologies using Cadence or Synopsys tools. The engineer will collaborate closely with circuit designers and other teams to meet project specifications and timelines, and will be responsible for floor planning, custom layout, and verifying compliance with design rules and schematics, including DRC, LVS, ANT, LUP, ESD, and PERC. Additionally, maintaining detailed documentation of layout methodologies, design decisions, and verification results is essential.

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 3-5+ years of relevant professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 2-3+ years of experience is preferred.
• Experience in analog/mixed-signal layout design for deep sub-micron CMOS circuits.
• Familiarity with advanced process technologies and FinFET is a plus.
• Proficient in block level floor planning and capable of driving the project through tape-out.
• Proficiency in chip level floor planning a plus.
• Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption.
• Understanding techniques to manage IR drop, RC delay, electro-migration, self-heating, and crosstalk.
• Experience with full chip layout and verification.
• Proficiency with CAD tools such as Cadence 'Virtuoso,' Mentor Graphics 'Calibre,' or Synopsys 'Custom Compiler.'
• Strong proficiency in interpreting DRC, ERC, LVS, LUP, and PERC reports.
• Ability to work independently with strong analytical skills, creative thinking, and self-motivation.
• Ability to work across teams.
• Strong communication skills.

Nice To Haves

• Proficiency in chip level floor planning.
• Familiarity with advanced process technologies and FinFET.

Responsibilities

• Design and optimize analog mixed-signal layouts such as high-speed ADCs, PLLs, bandgap voltage references, LDOs, high-speed I/O circuits, general I/Os, and ESD structures in deep sub-micron CMOS technologies.
• Collaborate closely with circuit designers and other teams to meet project specifications and timelines.
• Responsible for floor planning, custom layout, and verifying compliance with design rules and schematics, including DRC, LVS, ANT, LUP, ESD, and PERC.
• Maintain detailed documentation of layout methodologies, design decisions, and verification results.

Benefits

• Flexible time off.
• 401k.
• Year-end shutdown.
• Floating holidays.
• Paid time off to volunteer.

What This Job Offers

• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees