Senior Staff Digital Design Engineer - Wireline PHYs

Marvell-posted 4 months ago
$124,420 - $186,400/Yr
Full-time • Senior
Santa Clara, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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As a Digital IC Design Senior Staff Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. As a Senior Staff Digital Design Engineer you'll be focusing on system-level digital design and integration of wireline PHY IP for high-performance SoCs and ASICs. You will be responsible for architecting and implementing digital control, adaptation, DSP, and datapath logic enabling seamless PHY operation within larger system architectures, with an emphasis on embedded microcontroller integration, bus protocols, and system validation.

  • Architect and implement RTL for digital control, DSP blocks, digital datapath, and adaptation engines of PHY IP targeting SerDes, Die-to-Die, and Parallel Optics applications.
  • Design and verify bus interfaces (APB, AHB, AXI) and register maps for microcontroller communication and firmware control.
  • Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments.
  • Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals, including DSP and datapath optimizations.
  • Support system bring-up activities, validation planning, and post-silicon debug with a focus on system-level interactions involving digital datapath and DSP logic.
  • Mentor junior engineers and contribute to improving design methodologies for PHY system integration, including DSP and datapath design best practices.
  • Master's degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.
  • Strong RTL design expertise in Verilog/SystemVerilog, with a focus on digital control blocks, DSP, digital datapath, and bus protocols.
  • Solid understanding of logic synthesis, static timing analysis (STA), constraints development, and timing closure at block and chip levels.
  • Deep knowledge of CDC and RDC design principles.
  • Experience integrating PHY digital blocks, including DSP and datapath modules, with embedded microcontrollers, including interrupt and event handling.
  • Familiarity with scripting for design automation (Python, TCL, Perl).
  • Proven problem-solving and debug experience at system level, including post-silicon validation, particularly for DSP and datapath components.
  • Understanding of firmware-hardware co-design and system bring-up tools.
  • Flexible time off
  • 401k
  • Year-end shutdown
  • Floating holidays
  • Paid time off to volunteer
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