Senior Staff Design Verification Engineer

Marvell Technology • Santa Clara, CA

89d • $124,420 - $186,400

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading-edge data processing silicon platforms for AI, accelerated computing, cloud data center, and telecom customers. The group focuses on delivering innovative technology in diverse fast-growing product lines that encompass high performance design, advanced die-to-die and packaging technology, and optimized low-power techniques.

Requirements

• BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering.
• 5-10 years of relevant professional experience.
• Background in creating test plans and designing test bench architectures that are hierarchical, reusable and scalable.
• Background in SOC verification and test bench development using UVM and System Verilog, object oriented programming, and constrained random methods.
• Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.

Nice To Haves

• Effective communication and teamwork skills.
• Mindset for high quality and attention to detail.
• Independent learner, proactive in problem solving and finding solutions.

Responsibilities

• Architect and develop a functional verification environment, including reference models and bus-functional monitors and drivers.
• Write a verification test plan that employs random techniques, directed testing and coverage analysis to thoroughly check functional correctness and performance.
• Develop a testbench using UVM, System Verilog, C/C++, and DPI.
• Perform verification at different levels of hierarchy including block/unit, subsystem, and SOC levels.
• Work closely with logic designers to ensure the test plan is complete, debug simulation failures, and resolve issues.

Benefits

• Flexible time off.
• 401k.
• Year-end shutdown.
• Floating holidays.
• Paid time off to volunteer.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree