Senior SoC Methodology Architect, VLSI Physical Design

NVIDIA • Santa Clara, CA

13h • Hybrid

About The Position

NVIDIA powers the world's most advanced AI systems, autonomous vehicles, and data centers with industry-leading GPUs and accelerators. Delivering these breakthrough chips requires world-class physical design execution and deep expertise in EDA tool application. Our Physical Design Applications team partners directly with design teams to enable successful tape-outs through expert floorplan development, tool optimization, and hands-on technical support. We are looking for a Senior SoC Methodology Architect with expertise in floorplanning, early feasibility analysis, placement, routing, and methodology development. You will work closely with chip architects, EDA tool developers, and design leads to create and enhance floorplans in the early stages of chip development. This role requires creativity and the ability to work independently. It offers exceptional intellectual freedom and the chance to explore various responsibilities. If you enjoy working in multiple technical areas and want to see your contributions, come to life in top-tier AI hardware, this opportunity is perfect for you!

Requirements

• BS, MS, in Electrical Engineering, Computer engineering, Computer Science or equivalent experience
• A deep hardware engineering background with a concentration in chip floorplan, placement, routing and design analysis
• Experience with EDA tools, floorplanning and physical design methodologies (flow and tool development)
• 4+ years of relevant work experience
• Strong problem solving and analysis skills
• Understanding of Verilog and synthesis
• Python, Perl and C/C++ programming language experience
• Strong communication and interpersonal skills

Nice To Haves

• Experience in chip-level floor planning and physical design
• Familiarity in Python scripting and development
• Experience in collaborating across multiple teams
• A tenacity for solving complex challenges

Responsibilities

• Define and optimize top-level floorplan, including die size estimation, route planning and hierarchy definition and efficient partitioning
• Drive internal tools and top-level floorplan methodologies for chip automation
• Facilitate rapid analysis, and ensure the efficient execution of new chips on advanced process technologies.
• Collaborate with tool developers, architects, designers, and the top-level integration team to proactively identify and resolve issues.
• Examine and evaluate floorplans to detect potential issues and explore automated solutions.
• Support multi-functional development, integration, providing guidance and technical support to internal partners.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior